( en | de | ru )

 

Disambiguation of "Newton, A. Richard"

Author of the publication

copydeleteadd this publication to your clipboard
Highlights of VLSI Research at Berkeley.

, , and . FJCC, page 894-897. IEEE Computer Society, (1986)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Newton A Perrin

Robert Newton

Lionel Newton

Newton Maruyama

Newton Spolaôr

 

Other publications of authors with the same name

On the Verification of Sequential Machines at Differing Levels of Abstraction., , and . DAC, page 271-276. IEEE Computer Society Press / ACM, (1987)WELD - An Environment for Web-based Electronic Design., , and . DAC, page 146-151. ACM Press, (1998)Test generation for sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (10): 1081-1093 (1988)Algorithms for the transient simulation of lossy interconnect., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (1): 96-104 (1994)Algorithms for hardware allocation in data path synthesis., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (7): 768-781 (1989)System-level design: orthogonalization of concerns andplatform-based design., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (12): 1523-1543 (2000)A synthesis and optimization procedure for fully and easily testable sequential machines., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (10): 1100-1107 (1989)Sequential test generation and synthesis for testability at the register-transfer and logic levels., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (5): 579-598 (1993)The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (12): 1286-1298 (1989)Decomposition and factorization of sequential finite state machines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (11): 1206-1217 (1989)