Author of the publication

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.

, , , , , , and . ICCAD, page 74:1-74:8. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity., , , , , , , , and . IEEE J. Solid State Circuits, 58 (7): 1885-1897 (2023)FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory., , , , , , and . ICCAD, page 74:1-74:8. IEEE, (2020)Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA., , , , , , and . FPT, page 1-9. IEEE, (2021)Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 33:1-33:25 (June 2023)Efficient continual learning at the edge with progressive segmented training., , , , , , , , and . Neuromorph. Comput. Eng., 2 (4): 44006 (December 2022)A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification., , , , , , , , and . ESSCIRC, page 89-92. IEEE, (2022)FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix., , , , , and . DATE, page 1-6. IEEE, (2023)