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Disambiguation of "Burg, Andreas"

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Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 21 (4): 59:1-59:25 (2016)

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Andreas Burg

Andreas Marzell Burg

Josef Burg

Richard Burg

Arnold Burg

 

Other publications of authors with the same name

Silicon implementation of an MMSE-based soft demapper for MIMO-BICM., , , , , and . ISCAS, IEEE, (2006)Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture., , and . IACR Cryptology ePrint Archive, (2012)LoRa Digital Receiver Analysis and Implementation., , , and . CoRR, (2018)Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices., , , , , , , , , and . IEEE Des. Test, 37 (2): 84-92 (2020)An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications., , , , , and . IEEE J. Solid State Circuits, 53 (7): 2136-2148 (2018)Adding Indoor Capacity Without Fiber Backhaul: A mmWave Bridge Prototype., , and . CoRR, (2021)OpenCSI: An Open-Source Dataset for Indoor Localization Using CSI-Based Fingerprinting., , , and . CoRR, (2021)GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (12): 2042-2046 (2019)A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (4): 1245-1256 (2018)Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes., , , and . ACSCC, page 1137-1142. IEEE, (2008)