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Disambiguation of "Ferreira, Ricardo S."

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A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal.

, , , , , and . ACM Trans. Reconfigurable Technol. Syst., 8 (2): 9:1-9:16 (2015)

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Ana Helena Ferreira Ferreira

William Ferreira

Yvonne Ferreira

Jennifer Ferreira

Nelson Ferreira

 

Other publications of authors with the same name

READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications., , , , , , , and . ACM Trans. Embed. Comput. Syst., 18 (5s): 56:1-56:20 (2019)A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design., , , , and . Trans. High Perform. Embed. Archit. Compil., (2019)Gene regulatory accelerators on cloud FPGA., , , , , and . Concurr. Comput. Pract. Exp., (2023)Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks., , , , and . J. Syst. Archit., 57 (8): 761-777 (2011)Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots., , , , , , , and . IEEE Des. Test, 39 (6): 147-155 (2022)Exploring Nanomagnetic Logic with Bennett Clocking., , , , and . SBCCI, page 1-6. IEEE, (2023)Google Colab CAD4U: Hands-On Cloud Laboratories for Digital Design., , , , and . ISCAS, page 1-5. IEEE, (2021)A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures., , , and . ISVLSI, page 61-66. IEEE Computer Society, (2007)Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks., , , and . SBCCI, page 17:1-17:7. ACM, (2015)A run-time modulo scheduling by using a binary translation mechanism., , , , , and . ICSAMOS, page 75-82. IEEE, (2014)