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Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.

J. Olivito, F. Serrano, J. Clemente, H. Mecha, and J. Resano. IET Comput. Digit. Tech., 12 (4): 150-157 (2018)

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Javier Manero

Javier Jáurequi

Javier Dreyer

Javier Papa

Javier Arpón

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Memory hierarchy for high-performance and energyaware reconfigurable systems.E. Ramo, J. Resano, D. Mozos, and F. Catthoor. IET Comput. Digit. Tech., 1 (5): 565-571 (2007)Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms.J. Resano, D. Verkest, D. Mozos, S. Vernalde, and F. Catthoor. FCCM, page 278-279. IEEE Computer Society, (2003)Inference in Supervised Spectral Classifiers for On-Board Hyperspectral Imaging: An Overview.A. Alcolea, M. Paoletti, J. Haut, J. Resano, and A. Plaza. Remote. Sens., 12 (3): 534 (2020)FPGA support for satellite computations of hyper spectral images.C. González, D. Mozos, and J. Resano. FPL, page 715-716. IEEE, (2009)Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.J. Resano, D. Mozos, D. Verkest, S. Vernalde, and F. Catthoor. FPL, volume 2778 of Lecture Notes in Computer Science, page 585-594. Springer, (2003)Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.J. Olivito, F. Serrano, J. Clemente, H. Mecha, and J. Resano. IET Comput. Digit. Tech., 12 (4): 150-157 (2018)Reducing the reconfiguration overhead: a survey of techniques.E. Ramo, J. Resano, D. Mozos, and F. Catthoor. ERSA, page 191-194. CSREA Press, (2007)Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems.J. Clemente, R. Gran, A. Chocano, C. del Prado, and J. Resano. IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 530-543 (2016)A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems.J. Clemente, J. Resano, C. González, and D. Mozos. IEEE Trans. Very Large Scale Integr. Syst., 19 (7): 1263-1276 (2011)An FPGA-based specific processor for Blokus Duo.J. Olivito, C. González, and J. Resano. FPT, page 502-505. IEEE, (2013)

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Disambiguation of "Resano, Javier"

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Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.

Please choose a person to relate this publication to

Javier Manero

Javier Jáurequi

Javier Dreyer

Javier Papa

Javier Arpón

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Resano, Javier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.

Please choose a person to relate this publication to

Javier Manero

Javier Jáurequi

Javier Dreyer

Javier Papa

Javier Arpón

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.