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17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 494-496. IEEE, (2018)5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 110-112. IEEE, (2020)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 224-226. IEEE, (2020)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 234-236. IEEE, (2020)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1657-1667 (2009)Crosstalk-insensitive via-programming ROMs using content-aware design framework., , и . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (6): 443-447 (2006)A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing., , , , , , , , , и . IEEE J. Solid State Circuits, 51 (11): 2786-2798 (2016)A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 52 (1): 218-228 (2017)