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Change-point detection method on 100 Gb/s ethernet interface., , , and . ANCS, page 245-246. ACM, (2014)Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring., , , and . FPL, page 1-4. IEEE, (2014)Application specific processor with high level synthesized instructions (abstract only)., and . FPGA, page 246. ACM, (2014)Enhanced Flow Monitoring with P4 Generated Flexible Packet Parser., , , and . AIMS, page 21-32. IFIP, (2018)Architecture of Effective High-Speed Network Stream Merger., , and . DSD, page 459-464. IEEE Computer Society, (2014)Line rate programmable packet processing in 100Gb networks., , , and . FPL, page 1. IEEE, (2017)Verification of Generated RTL from P4 Source Code., , and . ICNP, page 444-445. IEEE Computer Society, (2018)Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput., , , , , and . FPGA, page 249-258. ACM, (2018)P4-To-VHDL: Automatic generation of high-speed input and output network blocks., , , and . Microprocess. Microsystems, (2018)Accelerated DDoS Attacks Mitigation using Programmable Data Plane., , , and . ANCS, page 1-3. IEEE, (2019)