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Automatic Parallelization of Compiled Event Driven VHDL Simulation.

, , and . IEEE Trans. Computers, 51 (4): 380-394 (2002)

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Automatic Parallelization of Compiled Event Driven VHDL Simulation., , and . IEEE Trans. Computers, 51 (4): 380-394 (2002)Improving Locality Using a Graph-Based Technique for Detecting Memory Layouts of Arrays., , , and . PPSC, (1999)Processor Tagged Descriptors: A Data Structure for Compiling for Distributed-Memory Multicomputers., , and . IFIP PACT, volume A-50 of IFIP Transactions, page 123-132. North-Holland, (1994)I/O Embedding in Hypercubes., and . ICPP (1), page 331-338. Pennsylvania State University Press, (1988)Functional abstraction of logic gates for switch-level simulation., , , and . EURO-DAC, page 329-333. EEE Computer Society, (1991)Design and Evaluation of Hardware Strategies for Reconfiguring Hypercubes and Meshes Under Faults., and . IEEE Trans. Computers, 43 (7): 841-848 (1994)The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive., and . IEEE Trans. Computers, 38 (1): 30-46 (1989)Potential-NRG: Placement with Incomplete Data., , and . DAC, page 279-282. ACM Press, (1998)Optimization by Simulated Evolution with Applications to Standard Cell Placement., and . DAC, page 20-25. IEEE Computer Society Press, (1990)Streaming Implementation of the ZLIB Decoder Algorithm on an FPGA., , and . ISCAS, page 2329-2332. IEEE, (2009)