( en | de | ru )

 

Disambiguation of "Cheng, Chung-Kuan"

Author of the publication

copydeleteadd this publication to your clipboard
Block placement with symmetry constraints based on the O-tree non-slicing representation.

, , , and . DAC, page 464-467. ACM, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chung-hsin Cheng

Yuan-Chung Cheng

Wen Chung Cheng

Cheng Han Chung

Chung-tao Cheng

 

Other publications of authors with the same name

Predicting the worst-case voltage violation in a 3D power network., , , , , and . SLIP, page 93-98. ACM, (2009)Worst-case performance prediction under supply voltage and temperature variation., , , and . SLIP, page 91-96. ACM, (2010)Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing., , , , and . SLIP, page 71-76. ACM, (2003)Placement and beyond in honor of Ernest S. Kuh.. ISPD, page 5-8. ACM, (2011)Stairway compaction using corner block list and its applications with rectilinear blocks., , , , , and . ACM Trans. Design Autom. Electr. Syst., 9 (2): 199-211 (2004)Layer minimization in escape routing for staggered-pin-array PCBs., , , and . ASP-DAC, page 187-192. IEEE, (2013)A new layout-driven timing model for incremental layout optimization., , and . ASP-DAC, page 127-131. IEEE, (1997)A multi-level transmission line network approach for multi-giga hertz clock distribution., and . ASP-DAC, page 103-106. ACM Press, (2005)Floorplanning with abutment constraints based on corner block list., , , , , and . Integr., 31 (1): 65-77 (2001)Reliability aware through silicon via planning for 3D stacked ICs., , , , , , , and . DATE, page 288-291. IEEE, (2009)