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A design platform for 90-nm leakage reduction techniques.

P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, J. Dong, D. Scott, B. Pitts, C. Raibaut, and U. Ko. DAC, page 549-550. ACM, (2005)

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David Allen Hughes

Jula Hughes

Hugh Skyhawk

Hugh Cardon

Hugh MacCauley

Other publications of authors with the same name

2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.H. Mair, E. Wang, A. Nayak, R. Lagerquist, L. Chou, G. Gammie, H. Chen, L. Yong, M. Rahman, J. Wiedemeier and 9 other author(s). ISSCC, page 50-52. IEEE, (2020)Solutions for logic and processor core design at the 45nm technology node & and below.P. Royannez, H. Mair, M. Clinton, and U. Ko. ICECS, page 923-926. IEEE, (2007)A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC.A. Nayak, H. Chen, H. Mair, R. Lagerquist, T. Chen, A. Rajagopalan, G. Gammie, R. Madhavaram, M. Jagota, C. Chung and 16 other author(s). ISSCC, page 50-52. IEEE, (2022)Session 4 Overview: Processors Digital Architectures and Systems Subcommittee.S. Mathew, S. Das, and H. Mair. ISSCC, page 52-53. IEEE, (2021)Session 17 overview: SRAM.H. Mair, and A. Kawasumi. ISSCC, page 304-305. IEEE, (2016)An architecture of high-performance frequency and phase synthesis.H. Mair, and L. Xiu. IEEE J. Solid State Circuits, 35 (6): 835-846 (2000)A design platform for 90-nm leakage reduction techniques.P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, J. Dong and 4 other author(s). DAC, page 549-550. ACM, (2005)Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.A. Joy, H. Mair, H. Lee, A. Feldman, C. Portmann, N. Bulman, E. Crespo, P. Hearne, P. Huang, B. Kerr and 10 other author(s). ISSCC, page 350-351. IEEE, (2011)SE1: What Technologies Will Shape the Future of Computing?H. Mair, S. Shiratake, E. Karl, T. Burd, J. Chang, D. Marr, S. Naffziger, H. Corporaal, K. Takeuchi, and N. Shanbhag. ISSCC, page 537-538. IEEE, (2021)14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU.C. Lu, B. Huang, M. Chen, O. Tsai, A. Tsai, E. Fang, Y. Cho, H. Chen, P. Kao, E. Wang and 2 other author(s). ISSCC, page 260-262. IEEE, (2024)

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Disambiguation of "Mair, Hugh"

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A design platform for 90-nm leakage reduction techniques.

Please choose a person to relate this publication to

David Allen Hughes

Jula Hughes

Hugh Skyhawk

Hugh Cardon

Hugh MacCauley

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mair, Hugh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A design platform for 90-nm leakage reduction techniques.

Please choose a person to relate this publication to

David Allen Hughes

Jula Hughes

Hugh Skyhawk

Hugh Cardon

Hugh MacCauley

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A design platform for 90-nm leakage reduction techniques.