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Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (5): 2028-2036 (мая 2023)Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , и . FPGA, стр. 262. ACM, (2015)Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors., и . VLSI-SoC, стр. 107-112. IEEE, (2018)GMS: Generic memristive structure for non-volatile FPGAs., , , , и . VLSI-SoC, стр. 94-98. IEEE, (2012)3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs., , , , и . VLSI-SoC (Selected Papers), том 621 из IFIP Advances in Information and Communication Technology, стр. 279-300. Springer, (2020)Emerging reconfigurable nanotechnologies: can they support future electronics?, , , , , , , и . ICCAD, стр. 13. ACM, (2018)A high-performance low-power near-Vt RRAM-based FPGA., , и . FPT, стр. 207-214. IEEE, (2014)GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment., , , , , , и . MICRO, стр. 334-346. ACM, (2019)A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors., , , и . VLSI-SoC (Selected Papers), том 586 из IFIP Advances in Information and Communication Technology, стр. 307-322. Springer, (2019)Multiple Independent Gate FETs: How many gates do we need?, , , , и . ASP-DAC, стр. 243-248. IEEE, (2015)