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Stochastic operational matrix of Chebyshev wavelets for solving multi-dimensional stochastic Itô-Volterra integral equations.

, and . Int. J. Wavelets Multiresolution Inf. Process., 17 (3): 1950007:1-1950007:16 (2019)

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A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing., , , , and . ANTS, page 1-6. IEEE, (2018)Worst Case O(N) Comparison-Free Hardware Sorting Engine., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3332-3345 (2022)An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup., , and . Photonic Netw. Commun., 32 (3): 359-371 (2016)Stochastic operational matrix of Chebyshev wavelets for solving multi-dimensional stochastic Itô-Volterra integral equations., and . Int. J. Wavelets Multiresolution Inf. Process., 17 (3): 1950007:1-1950007:16 (2019)A stochastic operational matrix method for numerical solutions of mixed stochastic Volterra-Fredholm integral equations., and . Int. J. Wavelets Multiresolution Inf. Process., 18 (2): 2050005:1-2050005:13 (2020)k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (5): 1438-1449 (May 2023)A Comparison-free Hardware Sorting Engine., , and . ISVLSI, page 586-591. IEEE, (2019)SRAM based longest prefix matching approach for multigigabit IP processing., , and . IEEE ANTS, page 1-6. IEEE, (2015)$O(N)$O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform., and . IEEE Trans. Computers, 72 (7): 2080-2093 (July 2023)Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing., , and . IEEE Trans. Computers, 71 (6): 1261-1275 (2022)