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Physical Design Variation in Relative Timed Asynchronous Circuits.

, и . ISVLSI, стр. 278-283. IEEE Computer Society, (2017)

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Другие публикации лиц с тем же именем

Physical Design Variation in Relative Timed Asynchronous Circuits., и . ISVLSI, стр. 278-283. IEEE Computer Society, (2017)Learning Based Timing Closure on Relative Timed Design., , и . VLSI-SoC (Selected Papers), том 621 из IFIP Advances in Information and Communication Technology, стр. 133-148. Springer, (2020)Post Quantum Blockchain Based Lightweight Edge Server Handover Authentication Key Agreement Protocol for Vehicular Communication System., , , , , и . ICCCNT, стр. 1-6. IEEE, (2023)Path Based Timing Validation for Timed Asynchronous Design., , и . VLSID, стр. 511-516. IEEE Computer Society, (2016)Automatic Timing Closure for Relative Timed Designs., и . VLSI-SOC, стр. 82-87. IEEE, (2020)