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Physical Design Variation in Relative Timed Asynchronous Circuits., and . ISVLSI, page 278-283. IEEE Computer Society, (2017)Learning Based Timing Closure on Relative Timed Design., , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 133-148. Springer, (2020)Post Quantum Blockchain Based Lightweight Edge Server Handover Authentication Key Agreement Protocol for Vehicular Communication System., , , , , and . ICCCNT, page 1-6. IEEE, (2023)Path Based Timing Validation for Timed Asynchronous Design., , and . VLSID, page 511-516. IEEE Computer Society, (2016)Automatic Timing Closure for Relative Timed Designs., and . VLSI-SOC, page 82-87. IEEE, (2020)