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Disambiguation of "Park, Kwanseo"

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A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology.

, , , , , , , , , , and . VLSI Technology and Circuits, page 34-35. IEEE, (2022)

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Rosemary Park

Sungjune Park

Jinhyung Park

Kwan Park

Shinja Park

 

Other publications of authors with the same name

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS., , , , , , and . VLSI Circuits, page 194-. IEEE, (2019)A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS., , , , , , , , , and 1 other author(s). ISCAS, page 1-5. IEEE, (2024)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS., , , , , , , and . ISSCC, page 128-130. IEEE, (2021)A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS., , , , and . A-SSCC, page 1-4. IEEE, (2015)A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 34-35. IEEE, (2022)A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration., , , , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2525-2538 (2021)A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS., , , , , , and . ISCAS, page 2389-2392. IEEE, (2015)A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line., , , , , and . ESSCIRC, page 447-450. IEEE, (2014)6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS., , , and . ISSCC, page 124-126. IEEE, (2020)