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2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions., and . VLSI-SOC, page 432-438. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)A new inverse discrete wavelet packet transform architecture., , , , and . ISSPA (2), page 443-446. IEEE, (2003)0-7803-7946-2.2D-DCT on FPGA by polynomial transformation in two-dimensions., , , and . ISCAS (3), page 365-368. IEEE, (2004)An active methodology for teaching electronic systems design., , , , and . IEEE Trans. Educ., 49 (3): 355-359 (2006)Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices., , , and . Microprocess. Microsystems, 28 (9): 509-518 (2004)FPGA Custom DSP for ECG Signal Analysis and Compression., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 954-958. Springer, (2004)Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management., , , and . Microprocess. Microsystems, 32 (2): 68-78 (2008)High-speed, low-complexity fir filter using multiplier block reduction and polyphase decomposition., and . ISCAS, page 367-370. IEEE, (2000)Fast FPGA-based pipelined digit-serial/parallel multipliers., , , and . ISCAS (1), page 482-485. IEEE, (1999)Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA., , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 533-542. Springer, (2003)