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Virtual-scan: a novel approach for software-based self-testing of microprocessors.

, , and . ISCAS (5), page 237-240. IEEE, (2003)

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Timing Error Detection and Correction by Time Dilation., , and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 271-285. Springer, (2008)Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (7): 926-931 (2008)Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing., and . ISVLSI (Selected papers), volume 105 of Lecture Notes in Electrical Engineering, page 217-230. Springer, (2010)A Robust and Reconfigurable Multi-mode Power Gating Architecture., , , and . VLSI Design, page 280-285. IEEE Computer Society, (2011)Self-exercising self testing k-order comparators., and . VTS, page 216-221. IEEE Computer Society, (1997)Novel Single and Double Output TSC Berger Code Checkers., and . VTS, page 348-353. IEEE Computer Society, (1998)Low Power Test-Compression for High Test-Quality and Low Test-Data Volume., and . Asian Test Symposium, page 46-53. IEEE Computer Society, (2011)On the Design of Self-Testing Checkers for Modified Berger Codes., , and . IOLTW, page 153-157. IEEE Computer Society, (2001)Two-dimensional time-division multiplexing for 3D-SoCs., , , and . ETS, page 1-6. IEEE, (2016)Recent advances in single- and multi-site test optimization for DVS-based SoCs., and . DTIS, page 1-6. IEEE, (2014)