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Disambiguation of "Morie, Takashi"

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Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.

, , , , , , , , , and . ASP-DAC, page 690-695. IEEE, (2009)

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Takashi Seki

Rolf Morié

Takashi Iwata

Takashi Numaguchi

Takashi Tsuno

 

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A pixel-parallel state-propagation algorithm with self-update of propagation direction for subjective contour generation., and . ISPACS, page 53-56. IEEE, (2015)Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links., , and . JRNAL, 4 (1): 91-96 (2017)Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation., , and . ICANN (1), volume 9886 of Lecture Notes in Computer Science, page 391-398. Springer, (2016)FPGA Implementation of Autoencoders Having Shared Synapse Architecture., , and . ICONIP (1), volume 9947 of Lecture Notes in Computer Science, page 231-239. (2016)A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation., , and . ICONIP (6), volume 10639 of Lecture Notes in Computer Science, page 821-829. Springer, (2017)A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing., , , and . IEEE Access, (2022)Gabor-Type Filtering using Transient States of Cellular Neural Networks., , and . Intell. Autom. Soft Comput., 10 (2): 95-104 (2004)Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3640-3644 (2022)Video Monitoring of Slope Failure Using Spatiotemporal Gabor Filtering., , , , , and . SMC, page 960-965. IEEE, (2009)A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design., , , and . CoRR, (2020)