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Disambiguation of "Nakamura, Toshiki"

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12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition.

, , , and . CICC, page 1-4. IEEE, (2017)

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Shin'ichiro Nakamura

Makoto Nakamura

Akira Nakamura

Hatsuo Nakamura

Hideki Nakamura

 

Other publications of authors with the same name

3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition., , , and . IEEE J. Solid State Circuits, 54 (6): 1800-1811 (2019)9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories., , and . CICC, page 1-4. IEEE, (2018)Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network., , , , and . ISCAS, page 1-5. IEEE, (2018)An on-chip, electricity-free and single-layer pressure sensor for microfluidic applications., , and . IROS, page 165-170. IEEE, (2015)Description and Discussion on DCASE2020 Challenge Task2: Unsupervised Anomalous Sound Detection for Machine Condition Monitoring., , , , , , , , , and 1 other author(s). DCASE, page 81-85. (2020)Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs., , , , and . IRPS, page 7-1. IEEE, (2018)Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition., , , and . ISCAS, page 1-5. IEEE, (2018)Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing., , , , , , and . A-SSCC, page 231-234. IEEE, (2019)Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories., , and . IEEE J. Solid State Circuits, 54 (3): 745-754 (2019)Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x., , , and . ESSDERC, page 150-153. IEEE, (2018)