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An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.

H. An, S. Schiferl, S. Venkatesan, T. Wesley, Q. Zhang, J. Wang, K. Choo, S. Liu, B. Liu, Z. Li, L. Gong, H. Zhong, D. Blaauw, R. Dreslinski, H. Kim, and D. Sylvester. IEEE J. Solid State Circuits, 56 (4): 1071-1081 (2021)

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Prem Choontanom

Suma Choorapoikayil

Noppon Choosri

Ping Chook

Seung Yeon Choo

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A 184nW, 121µg/√Hz Noise Floor Triaxial MEMS Accelerometer with Integrated CMOS Readout Circuit and Variation-Compensated High Voltage MEMS Biasing.Y. Peng, S. Jeong, K. Choo, Y. Kim, L. Chen, R. Rothe, L. Xu, I. Gurin, O. Oliaei, V. Tsinker and 4 other author(s). VLSI Technology and Circuits, page 84-85. IEEE, (2022)An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation.Y. Peng, S. Jeong, K. Choo, Y. Kim, L. Chen, R. Rothe, L. Xu, I. Gurin, O. Oliaei, M. Thompson and 4 other author(s). IEEE J. Solid State Circuits, 59 (7): 2219-2235 (July 2024)A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge.H. An, S. Venkatesan, S. Schiferl, T. Wesley, Q. Zhang, J. Wang, K. Choo, S. Liu, B. Liu, Z. Li and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS.C. Kye, and K. Choo. A-SSCC, page 1-3. IEEE, (2023)A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor.J. Kim, W. ki Jung, S. hyun Lim, Y. jin Park, W. Choi, Y. Kim, C. eun Kang, J. Shin, K. Choo, W. baek Lee and 9 other author(s). ISSCC, page 390-392. IEEE, (2012)14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC.K. Choo, H. An, D. Sylvester, and D. Blaauw. ISSCC, page 372-374. IEEE, (2021)An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.H. An, S. Schiferl, S. Venkatesan, T. Wesley, Q. Zhang, J. Wang, K. Choo, S. Liu, B. Liu, Z. Li and 6 other author(s). IEEE J. Solid State Circuits, 56 (4): 1071-1081 (2021)Reference Oversampling PLL Achieving -256-dB FoM and -78-dBc Reference Spur.J. Seol, K. Choo, D. Blaauw, D. Sylvester, and T. Jang. IEEE J. Solid State Circuits, 56 (10): 2993-3007 (2021)A 192 nW 0.02 Hz High Pass Corner Acoustic Analog Front-End with Automatic Saturation Detection and Recovery.R. Rothe, M. Cho, K. Choo, S. Jeong, D. Sylvester, and D. Blaauw. VLSI Circuits, page 1-2. IEEE, (2021)3.3 A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection.L. Xu, T. Jang, J. Lim, K. Choo, D. Blaauw, and D. Sylvester. ISSCC, page 62-64. IEEE, (2020)

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Disambiguation of "Choo, Kyojin"

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An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.

Please choose a person to relate this publication to

Prem Choontanom

Suma Choorapoikayil

Noppon Choosri

Ping Chook

Seung Yeon Choo

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Choo, Kyojin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.

Please choose a person to relate this publication to

Prem Choontanom

Suma Choorapoikayil

Noppon Choosri

Ping Chook

Seung Yeon Choo

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
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Chicago
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An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.