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Disambiguation of "Amirkhany, Amir"

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An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.

, , , , , and . CICC, page 1-4. IEEE, (2011)

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Manutschehr Amirfeyz

Iradj Amirzadeh-Asl

Mahmud Amirian-Khaffadjeh

Belal Amireh

Mansoor Anwer Ismail Amir

 

Other publications of authors with the same name

Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links., , , and . GLOBECOM, IEEE, (2006)A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration., , , , , , , , , and 1 other author(s). ISSCC, page 132-134. IEEE, (2012)A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link., , , , , , , , and . ISSCC, page 138-140. IEEE, (2012)A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS., , and . ISSCC, page 42-43. IEEE, (2013)Time-Variant Characterization and Compensation of Wideband Circuits., , , and . CICC, page 487-490. IEEE, (2007)Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication., , and . ICC, page 2799-2806. IEEE, (2004)An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface., , , , , and . CICC, page 1-4. IEEE, (2011)A new technique for characterization of digital-to-analog converters in high-speed systems., , , , and . DATE, page 433-438. EDA Consortium, San Jose, CA, USA, (2007)Power-efficient I/O design considerations for high-bandwidth applications., , , , , , , , and . CICC, page 1-8. IEEE, (2011)A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link., , , , , , , , and . ISSCC, page 138-140. IEEE, (2012)