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MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis.

P. SLPSK, M. Patnaik, S. Potluri, and V. Kamakoti. J. Low Power Electron., 14 (2): 285-301 (2018)

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Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors.Q. Tan, S. Potluri, and A. Aysu. ISCAS, page 1-5. IEEE, (2020)Synthesis of on-chip control circuits for mVLSI biochips.S. Potluri, A. Schneider, M. Horslev-Petersen, P. Pop, and J. Madsen. DATE, page 1799-1804. IEEE, (2017)DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks.F. Aydin, P. Kashyap, S. Potluri, P. Franzon, and A. Aysu. SAMOS, volume 12471 of Lecture Notes in Computer Science, page 262-280. Springer, (2020)Security of Microfluidic Biochip: Practical Attacks and Countermeasures.H. Chen, S. Potluri, and F. Koushanfar. ACM Trans. Design Autom. Electr. Syst., 25 (3): 27:1-27:29 (2020)SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation.S. Potluri, S. Kundu, A. Kumar, K. Basu, and A. Aysu. IACR Cryptol. ePrint Arch., (2021)DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests.S. Trinadh, C. Babu, S. Singh, S. Potluri, and V. Kamakoti. DATE, page 836-841. ACM, (2015)BioChipWork: Reverse Engineering of Microfluidic Biochips.H. Chen, S. Potluri, and F. Koushanfar. ICCD, page 9-16. IEEE Computer Society, (2017)LPScan: An algorithm for supply scaling and switching activity minimization during test.S. Potluri, S. Adireddy, C. Rajamanikkam, and S. Balachandran. ICCD, page 463-466. IEEE Computer Society, (2013)Scalable Scan-Chain-Based Extraction of Neural Network Models.S. Jiang, S. Potluri, and T. Ho. DATE, page 1-6. IEEE, (2023)Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing.S. Adireddy, S. Potluri, C. Babu, V. Kamakoti, and S. Singh. ACM Trans. Design Autom. Electr. Syst., 23 (1): 5:1-5:26 (2017)

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MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis.

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MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis.