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A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.

I. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, and H. Smith. DATE, page 144-149. IEEE Computer Society, (2004)

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Howard H Buxbaum

Howard H Rowley

Sabine H Smith

Howard Nelson

Howard Foster

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Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors.R. III, K. Barkley, M. Bowen, P. Camporese, A. Dansky, R. Hatch, D. Hoffman, M. Mayo, S. McCabe, T. McNamara and 6 other author(s). IBM J. Res. Dev., 43 (5): 681-706 (1999)Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.J. Warnock, Y. Chan, H. Harrer, S. Carey, G. Salem, D. Malone, R. Puri, J. Zitz, A. Jatkowski, G. Strevig and 15 other author(s). IEEE J. Solid State Circuits, 49 (1): 9-18 (2014)MCM technology and design for the S/390 G5 system.G. Katopis, W. Becker, T. Mazzawy, H. Smith, C. Vakirtzis, S. Kuppinger, B. Singh, P. Lin, J. Jr., G. Kihlmire and 3 other author(s). IBM J. Res. Dev., 43 (5): 621-650 (1999)IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology.B. Curran, Y. Chan, P. Wu, P. Camporese, G. Northrop, R. Hatch, L. Lacey, J. Eckhardt, D. Hui, and H. Smith. IBM J. Res. Dev., 46 (4-5): 631- (2002)R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip.H. Smith, A. Deutsch, S. Mehrotra, D. Widiger, M. Bowen, A. Dansky, G. Kopcsay, and B. Krauter. CICC, page 237-240. IEEE, (2001)A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.I. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, and H. Smith. DATE, page 144-149. IEEE Computer Society, (2004)A 5.2GHz microprocessor chip for the IBM zEnterprise™ system.J. Warnock, Y. Chan, W. Huott, S. Carey, M. Fee, H. Wen, M. Saccamango, F. Malgioglio, P. Meaney, D. Plass and 17 other author(s). ISSCC, page 70-72. IEEE, (2011)Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System.J. Warnock, Y. Chan, S. Carey, H. Wen, P. Meaney, G. Gerwig, H. Smith, Y. Chan, J. Davis, P. Bunce and 9 other author(s). IEEE J. Solid State Circuits, 47 (1): 151-163 (2012)A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis.G. Kopcsay, B. Krauter, D. Widiger, A. Deutsch, B. Rubin, and H. Smith. IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 695-711 (2002)On-chip wiring design challenges for gigahertz operation.A. Deutsch, P. Coteus, G. Kopcsay, H. Smith, C. Surovic, B. Krauter, D. Edelstein, and P. Restle. Proc. IEEE, 89 (4): 529-555 (2001)

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Disambiguation of "Smith, Howard H."

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A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.

Please choose a person to relate this publication to

Howard H Buxbaum

Howard H Rowley

Sabine H Smith

Howard Nelson

Howard Foster

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Smith, Howard H."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.

Please choose a person to relate this publication to

Howard H Buxbaum

Howard H Rowley

Sabine H Smith

Howard Nelson

Howard Foster

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.