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Analysis of the Task Superscalar Architecture Hardware Design.

, , , , and . ICCS, volume 18 of Procedia Computer Science, page 339-348. Elsevier, (2013)

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Design space exploration of hardware task superscalar architecture., and . J. Supercomput., 71 (9): 3567-3592 (2015)EELCM: An Energy Efficient Load-Based Clustering Method for Wireless Mobile Sensor Networks., and . Mob. Networks Appl., 24 (5): 1486-1498 (2019)Picos: A hardware runtime architecture support for OmpSs., , , , and . Future Gener. Comput. Syst., (2015)H2WNoC: A honeycomb hardware-efficient wireless network-on-chip architecture., and . Nano Commun. Networks, (2019)An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip., , , , and . J. Supercomput., 75 (2): 837-861 (2019)An Energy Efficient Autonomous Method for Coverage Optimization in Wireless Multimedia Sensor Networks., , and . Wireless Personal Communications, 99 (2): 717-736 (2018)Hybrid Dataflow/von-Neumann Architectures., , , and . IEEE Trans. Parallel Distributed Syst., 25 (6): 1489-1509 (2014)A low-power WNoC transceiver with a novel energy consumption management scheme for dependable IoT systems.. J. Parallel Distributed Comput., (February 2023)Hardware design of task superscalar architecture.. Polytechnic University of Catalonia, Spain, (2014)HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era., , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 304-316. Springer, (2018)