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Disambiguation of "Yamashina, Masakazu"

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Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.

, , , , , , , and . IEEE J. Solid State Circuits, 30 (6): 637-643 (June 1995)

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Gregorius-Masakazu Inugai

 

Other publications of authors with the same name

A Single-Chip Multiprocessor for Smart Terminals., , , and . IEEE Micro, 20 (4): 12-20 (2000)A 2000-MOPS embedded RISC processor with a Rambus DRAM controller., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (7): 1010-1021 (1999)Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI., , , , and . CICC, page 151-154. IEEE, (2000)A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 32 (11): 1807-1816 (1997)Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications., , , , , , , and . IEEE J. Solid State Circuits, 30 (6): 637-643 (June 1995)A 0.25-μm CMOS 0.9-V 100-MHz DSP core., , , , , , and . IEEE J. Solid State Circuits, 32 (1): 52-61 (1997)A current direction sense technique for multiport SRAM's., and . IEEE J. Solid State Circuits, 31 (4): 546-551 (1996)Guest editorial., and . IEEE J. Solid State Circuits, 36 (5): 724-725 (2001)A low-power W-CDMA demodulator using specially-designed micro-DSPs., , , , and . CICC, page 397-400. IEEE, (2002)An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU., , , , , , , , and . ICASSP, page 599-602. IEEE Computer Society, (1997)