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Scaling trends of on-chip power distribution noise., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (4): 386-394 (2004)QuCTS - Single-Flux Quantum Clock Tree Synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3346-3358 (2022)TEAM: ThrEshold Adaptive Memristor Model., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (1): 211-221 (2013)Low-voltage-swing monolithic dc-dc conversion., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 241-248 (2004)Clock distribution networks in synchronous digital integrated circuits.. Proc. IEEE, 89 (5): 665-692 (2001)On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits., , , and . SoCC, page 309-312. IEEE, (2005)Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor., and . ISCAS, page 1-5. IEEE, (2018)Link breaking methodology: mitigating noise within power networks., and . ACM Great Lakes Symposium on VLSI, page 129-134. ACM, (2012)Test point insertion for RSFQ circuits., and . ISCAS, page 1-4. IEEE, (2017)PMTJ Temperature Sensor Utilizing VCMA., and . ISCAS, page 1-5. IEEE, (2019)