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TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.

M. Cheng, L. Xia, Z. Zhu, Y. Cai, Y. Xie, Y. Wang, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 834-847 (2019)

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Yang Yang

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Increasing Compression Ratio of Low Complexity Compressive Sensing Video Encoder with Application-Aware Configurable Mechanism.S. Yu, F. Qiao, L. Luo, and H. Yang. CoRR, (2013)A Novel Reconfigurable Computing Architecture for Image Signal Processing Using Circuit-Switched NoC and Synchronous Dataflow Model.F. Li, F. Qiao, Q. Wei, and H. Yang. CoRR, (2013)A Survey of FPGA Based Neural Network Accelerator.K. Guo, S. Zeng, J. Yu, Y. Wang, and H. Yang. CoRR, (2017)Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system.B. Li, L. Xia, P. Gu, Y. Wang, and H. Yang. DAC, page 13:1-13:6. ACM, (2015)Nonparametric Topic Modeling with Neural Inference.X. Ning, Y. Zheng, Z. Jiang, Y. Wang, H. Yang, and J. Huang. CoRR, (2018)Modeling the Impact of Process Variation on Critical Charge Distribution.Q. Ding, R. Luo, H. Wang, H. Yang, and Y. Xie. SoCC, page 243-246. IEEE, (2006)Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA.K. Guo, L. Sui, J. Qiu, J. Yu, J. Wang, S. Yao, S. Han, Y. Wang, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (1): 35-47 (2018)Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.L. Xia, P. Gu, B. Li, T. Tang, X. Yin, W. Huangfu, S. Yu, Y. Cao, Y. Wang, and H. Yang. J. Comput. Sci. Technol., 31 (1): 3-19 (2016)Low-Cost Multi-Agent Navigation via Reinforcement Learning With Multi-Fidelity Simulator.J. Qiu, C. Yu, W. Liu, T. Yang, J. Yu, Y. Wang, and H. Yang. IEEE Access, (2021)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.Y. Chen, M. Lee, G. Dai, M. Zhou, N. Challapalle, T. Wang, Y. Yu, Y. Liu, Y. Wang, H. Yang and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)

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Disambiguation of "Yang, Huazhong"

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TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Huazhong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

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TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.