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Efficient Design and Evaluation of Countermeasures against Fault Attacks Using Formal Verification.

, , , and . CARDIS, volume 9514 of Lecture Notes in Computer Science, page 177-192. Springer, (2015)

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Efficient Design and Evaluation of Countermeasures against Fault Attacks Using Formal Verification., , , and . CARDIS, volume 9514 of Lecture Notes in Computer Science, page 177-192. Springer, (2015)A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking.. CHARME, volume 987 of Lecture Notes in Computer Science, page 328-342. Springer, (1995)An efficient refinement strategy exploiting component properties in a cegar process., , and . FDL, page 27-34. IEEE, (2012)Data Decision Diagrams for Petri Net Analysis., , , , and . ICATPN, volume 2360 of Lecture Notes in Computer Science, page 101-120. Springer, (2002)Using CTL formulae as component abstraction in a design and verification flow., and . ACSD, page 80-89. IEEE Computer Society, (2007)A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip., , and . HLDVT, page 203-210. IEEE Computer Society, (2006)CTL May Be Ambiguous When Model Checking Moore Machines., and . CHARME, volume 2860 of Lecture Notes in Computer Science, page 164-169. Springer, (2003)Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process., , and . FDL (Selected Papers), volume 265 of Lecture Notes in Electrical Engineering, page 17-36. Springer, (2012)Formal Verification of Timed VHDL Programs., , , , , and . FDL, page 80-85. ECSI, Electronic Chips & Systems design Initiative, (2010)FSM-based properties and abstraction of components., and . RSP, page 37-43. IEEE, (2014)