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Signal probability control for relieving NBTI in SRAM cells., , and . ISQED, page 660-666. IEEE, (2010)A Proposal for a Co-design Method in Control Systems Using Combination of Models., , , , and . IEICE Trans. Inf. Syst., 78-D (3): 237-247 (1995)Embedded System Design Using Soft-Core Processor and Valen-C., , , and . J. Inf. Sci. Eng., 14 (3): 587-603 (1998)High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree., , and . IEEE Trans. Computers, 34 (9): 789-796 (1985)Width and Depth of Combinational Logic Circuits.. Inf. Process. Lett., 13 (4/5): 191-194 (1981)Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment., , , and . IEICE Trans. Electron., 92-C (4): 483-491 (2009)An FPGA-based genetic algorithm machine (poster abstract)., , , , , , and . FPGA, page 218. ACM, (2000)An Interactive Simulation System for structured logic design - ISS., , , , , , , and . DAC, page 747-754. ACM/IEEE, (1982)Quantitative evaluation of unlinkable ID matching schemes., , , and . WPES, page 55-60. ACM, (2005)Power analysis techniques for SoC with improved wiring models., , , , , and . ISLPED, page 259-262. ACM, (2002)