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Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.

, , , , и . ATS, стр. 242-247. IEEE Computer Society, (2017)

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Combinational circuit fault diagnosis using logic emulation., , , , и . ISCAS (5), стр. 549-552. IEEE, (2003)A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume., , , , и . ISCIT, стр. 1-5. IEEE, (2017)Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory., и . ITC-Asia, стр. 1-6. IEEE, (2023)Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators., , , , , и . ATS, стр. 49-53. IEEE, (2022)A built-in supply current test circuit for electrical interconnect tests of 3D ICs., , , и . 3DIC, стр. 1-6. IEEE, (2014)Fault-Aware Dependability Enhancement Techniques for Flash Memories., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 28 (3): 634-645 (2020)Efficient test and repair architectures for 3D TSV-based random access memories., , , и . VLSI-DAT, стр. 1-4. IEEE, (2013)Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs., , , и . VLSI-DAT, стр. 1-4. IEEE, (2015)Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs., , и . Asian Test Symposium, стр. 308-313. IEEE Computer Society, (2012)A Multi-Faceted Approach towards Spam-Resistible Mail., , , , и . PRDC, стр. 208-218. IEEE Computer Society, (2005)