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Disambiguation of "Lu, Shyue-Kung"

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A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume.

, , , , and . ISCIT, page 1-5. IEEE, (2017)

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Lu Lu

Zigmas Kungys

Hans Kungl

Angela Brigitte Kung

Sebastian Küng

 

Other publications of authors with the same name

Combinational circuit fault diagnosis using logic emulation., , , , and . ISCAS (5), page 549-552. IEEE, (2003)A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume., , , , and . ISCIT, page 1-5. IEEE, (2017)Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults., , , , , and . J. Inf. Sci. Eng., 19 (4): 571-587 (2003)Fault-Aware Dependability Enhancement Techniques for Phase Change Memory., , , , and . J. Electron. Test., 37 (4): 503-513 (2021)Design-for-testability and fault-tolerant techniques for FFT processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (6): 732-741 (2005)Yield enhancement techniques for 3-dimensional random access memories., , and . Microelectron. Reliab., 52 (6): 1065-1070 (2012)Fault-Aware Dependability Enhancement Techniques for Flash Memories., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (3): 634-645 (2020)Defect Level Prediction Using Multi-Model Fault Coverage.. IEICE Trans. Inf. Syst., 87-D (6): 1488-1495 (2004)A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs., , , , , , and . IEICE Trans. Inf. Syst., 99-D (11): 2723-2733 (2016)A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs., , , , and . IEICE Trans. Inf. Syst., 101-D (8): 2053-2063 (2018)