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Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs.

, and . Microprocess. Microsystems, (2017)

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WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption., and . ACM Trans. Archit. Code Optim., 18 (4): 55:1-55:25 (2021)Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs., and . Microprocess. Microsystems, (2017)RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress., , , and . CODES+ISSS, page 8-10. IEEE, (2020)TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores., , and . ACM Trans. Embed. Comput. Syst., 23 (4): 61:1-61:31 (July 2024)TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture., , and . IPDPS, page 852-864. IEEE, (2024)A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip., , and . VDAT, page 1-6. IEEE, (2014)NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems., , and . SAMOS, volume 14385 of Lecture Notes in Computer Science, page 33-42. Springer, (2023)Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)., , and . DAC, page 1-6. IEEE, (2023)STIFF: thermally safe temperature effect inversion aware FinFET based multi-core., , and . CF, page 21-29. ACM, (2022)ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache., and . ASAP, page 171-174. IEEE, (2021)