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A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS., , , , , , and . CICC, page 1-4. IEEE, (2010)A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications., , , , , , and . ISSCC, page 458-615. IEEE, (2007)A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (11): 741-745 (2012)Chiplet Heterogeneous-Integration AI Processor., , , , , , , , , and 5 other author(s). ICEIC, page 1-2. IEEE, (2023)Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs., , , and . ISCAS, page 451-454. IEEE, (2000)A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter., , , , and . ASP-DAC, page 613-616. ACM, (2000)A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS., , , , and . ISSCC, page 456-615. IEEE, (2007)A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (7): 502-506 (2010)A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications., , , and . IEEE J. Solid State Circuits, 42 (12): 2688-2695 (2007)A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications., , , , , , , , and . CICC, page 497-500. IEEE, (2006)