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Disambiguation of "Kim, Jae-Joon"

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Technology-circuit co-design of asymmetric SRAM cells for read stability improvement.

, , and . CICC, page 1-4. IEEE, (2010)

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Joon-Young Kim

Nam-Joon Kim

Man Joon Kim

Joon-Soon Kim

Hyun-Joon Kim

 

Other publications of authors with the same name

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS., , , and . ISSCC, page 388-389. IEEE, (2008)Highly improved SNR differential sensing method using parallel operation signaling for touch screen application., , , and . A-SSCC, page 157-160. IEEE, (2014)Technology-circuit co-design of asymmetric SRAM cells for read stability improvement., , and . CICC, page 1-4. IEEE, (2010)A forward body-biased low-leakage SRAM cache: device and architecture considerations., , , and . ISLPED, page 6-9. ACM, (2003)BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks., , , , , , and . IEEE J. Solid State Circuits, 57 (6): 1924-1935 (2022)PVT-aware leakage reduction for on-die caches with improved read stability., , , and . IEEE J. Solid State Circuits, 41 (1): 170-178 (2006)Magnetic Induction Tomography Using Multi-Channel Phase-Domain Transceiver for Structural Health Monitoring., , , , , and . IEEE Trans. Instrum. Meas., (2022)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , and . Microelectron. J., 38 (8-9): 931-941 (2007)Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow., , and . ICCAD, page 1-9. IEEE, (2021)In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time., , , , and . DAC, page 1-6. IEEE, (2023)