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On-chip parallel and network-based systems., , and . Integr., (2015)PLAM: A Posit Logarithm-Approximate Multiplier., , , , , and . IEEE Trans. Emerg. Top. Comput., 10 (4): 2079-2085 (2022)Scalable load balancing congestion-aware Network-on-Chip router architecture., , and . J. Comput. Syst. Sci., 79 (4): 421-439 (2013)Designing quantum-dot cellular automata counters with energy consumption analysis., , , , and . Microprocess. Microsystems, 39 (7): 512-520 (2015)Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (9): 1788-1801 (2018)A formal approach to context scheduling for multicontext reconfigurable architectures., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 173-185 (2001)A framework for reconfigurable computing: task scheduling and context management., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 858-873 (2001)Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks., , , and . PDP, page 307-311. IEEE, (2020)Performance of symbolic applications on a parallel architecture., , , and . Int. J. Parallel Program., 16 (3): 183-214 (1987)Near-optimal message routing and broadcasting in faulty hypercubes., and . Int. J. Parallel Program., 19 (5): 405-423 (1990)