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Core architecture optimization for heterogeneous chip multiprocessors.

, , and . PACT, page 23-32. ACM, (2006)

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Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0., , and . MICRO, page 3-14. IEEE Computer Society, (2007)The role of optics in future high radix switch design., , , , , , and . ISCA, page 437-448. ACM, (2011)Hardware/Software Tradeoffs for Increased Performance., , , , and . ASPLOS, page 2-11. ACM Press, (1982)SIGARCH Computer Architecture News 10(2), SIGPLAN Notices 17(4).Complexity/Performance Tradeoffs with Non-Blocking Loads., and . ISCA, page 211-222. IEEE Computer Society, (1994)Tradeoffs in Two-Level On-Chip Caching., and . ISCA, page 34-45. IEEE Computer Society, (1994)FREE-p: Protecting non-volatile memory against both hard and soft errors., , , , , and . HPCA, page 466-477. IEEE Computer Society, (2011)Enterprise IT Trends and Implications for Architecture Research., and . HPCA, page 253-256. IEEE Computer Society, (2005)Design implications of memristor-based RRAM cross-point structures., , , and . DATE, page 734-739. IEEE, (2011)CACTI: an enhanced cache access and cycle time model., and . IEEE J. Solid State Circuits, 31 (5): 677-688 (1996)The Future Evolution of High-Performance Microprocessors.. HiPC, volume 3296 of Lecture Notes in Computer Science, page 5. Springer, (2004)