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Disambiguation of "Bertozzi, Davide"

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xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.

, , , , , and . DATE, page 1188-1193. IEEE Computer Society, (2005)

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Davide Pennino

Davide Cadamuro

Davide Batic

Davide Pagani

Davide Cantoni

 

Other publications of authors with the same name

Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels., and . AISTECS@HiPEAC, page 12-17. ACM, (2017)Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip., , , and . IET Comput. Digit. Tech., (2013)Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip., , , and . Embedded Systems Design and Verification, CRC Press, (2009)DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost., , , and . ARC, volume 9040 of Lecture Notes in Computer Science, page 419-426. Springer, (2015)Analyzing On-Chip Communication in a MPSoC Environment., , , , and . DATE, page 752-757. IEEE Computer Society, (2004)SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives., , , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration., , and . DATE, page 806-811. ACM, (2015)Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels., , , and . MCSoC, page 159-166. IEEE Computer Society, (2012)Low Power Error Resilient Encoding for On-Chip Data Buses., , and . DATE, page 102-109. IEEE Computer Society, (2002)Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework., , , , , , and . NOCS, page 107-116. IEEE Computer Society, (2008)