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Model-based Design of Efficient LDPC Decoder Architectures., , , and . ISTC, page 1-5. IEEE, (2018)Model-based Design of Hardware SC Polar Decoders for FPGAs., , , and . ACM Trans. Reconfigurable Technol. Syst., 13 (2): 10:1-10:27 (2020)Networked Self-adaptive Systems: An Opportunity for Configuring in the Large., , , , , , , and . ERSA, page 81-90. CSREA Press, (2009)Methodology to Adapt Neural Network on Constrained Device at Topology level., , , , , and . SiPS, page 1-6. IEEE, (2022)A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices., , and . IEEE Embed. Syst. Lett., 6 (2): 29-32 (2014)An Energy Efficient and Scalable Node Architecture for Sensor Network., , , and . NEWCAS, page 1-4. IEEE, (2021)Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices., , , and . J. Signal Process. Syst., 92 (7): 727-745 (2020)Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping., , , and . FPL, page 372-375. IEEE Computer Society, (2018)Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis., , , and . SiPS, page 242-247. IEEE, (2019)Modeling dynamic partial reconfiguration in the dataflow paradigm., and . SiPS, page 298-303. IEEE, (2014)