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Resource Management in Dataflow-Based Multithreaded Execution., , , and . J. Parallel Distributed Comput., 61 (5): 581-608 (2001)Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs., and . FPL, page 655-658. IEEE, (2008)Exploiting Locality in Hybrid Dataflow Programs., , and . Multithreaded Computer Architecture, volume 281 of The Kluwer International Series in Engineering and Computer Science, Kluwer / Springer, (1994)Power Efficient Instruction Caches for Embedded Systems., , and . SAMOS, volume 3553 of Lecture Notes in Computer Science, page 182-191. Springer, (2005)An Evaluation of Optimized Threaded Code Generation., , , and . IFIP PACT, volume A-50 of IFIP Transactions, page 37-46. North-Holland, (1994)Compiled multithreaded data paths on FPGAs for dynamic workloads., and . CASES, page 3:1-3:10. IEEE, (2013)FHAST: FPGA-Based Acceleration of Bowtie in Hardware., , , and . IEEE ACM Trans. Comput. Biol. Bioinform., 12 (5): 973-981 (2015)Techniques for synthesizing binaries to an advanced register/memory structure., , , and . FPGA, page 118-124. ACM, (2005)FPGA code accelerators - the compiler perspective., and . DAC, page 141:1-141:6. ACM, (2013)Exploring irregular memory accesses on FPGAs., , and . IA3@SC, page 31-34. ACM, (2011)