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A 50% duty-cycle correction circuit for PLL output., and . ISCAS (4), page 21-24. IEEE, (2002)Parallel bus systems using code-division multiple access technique., , and . ISCAS (2), page 240-243. IEEE, (2003)An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference., , , and . IEICE Trans. Electron., 94-C (6): 960-967 (2011)A Dynamic Dither Gain Control Technique for Multi-Level Delta-Sigma DACs with Multi-Stage Second Order Dynamic Element Matching., , and . IEICE Trans. Electron., 94-C (3): 346-352 (2011)Process modeling and simulation: boundary conditions for point defect-based impurity diffusion model., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (11): 1177-1183 (1990)A New Analog Correlator Circuit for DS-CDMA Wireless Applications., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (5): 1294-1301 (2003)Analytical design of a 0.5V 5GHz CMOS LC-VCO., , , , , and . IEICE Electron. Express, 6 (14): 1025-1031 (2009)A dual-band image-reject mixer for GPS with 64dB image rejection., , , and . ASP-DAC, page 541-542. IEEE Computer Society, (2004)CMOS phase-shift VCO for short-range wireless communication., , and . ISCAS (4), page 405-408. IEEE, (2002)A 0.5 V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier., , , , , and . IEICE Trans. Electron., 92-C (4): 564-575 (2009)