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Disambiguation of "Varadarajan, Keshavan"

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REDEFINE: Runtime reconfigurable polymorphic ASIC.

, , , , , , , , , , and . ACM Trans. Embed. Comput. Syst., 9 (2): 11:1-11:48 (2009)

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Balamurugan Varadarajan

Varadarajan Seshadri

Badri Varadarajan

Sriram Varadarajan

 

Other publications of authors with the same name

REDEFINE: Runtime reconfigurable polymorphic ASIC., , , , , , , , , and 1 other author(s). ACM Trans. Embed. Comput. Syst., 9 (2): 11:1-11:48 (2009)Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions., , , , , , and . MICRO, page 433-442. IEEE Computer Society, (2006)Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures., , , , and . ARC, volume 5453 of Lecture Notes in Computer Science, page 204-215. Springer, (2009)A Framework for QoS Adaptive Grid Meta Scheduling., , , , and . DEXA Workshops, page 292-296. IEEE Computer Society, (2005)Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture., , , , , , and . ICSAMOS, page 178-184. IEEE, (2010)Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform., , , , , , and . ISVLSI, page 161-166. IEEE Computer Society, (2010)REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures., , , , and . FPL, page 558-561. IEEE, (2007)Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network., , , , and . SoC, page 1-4. IEEE, (2008)A Method for Flexible Reduction over Binary Fields using a Field Multiplier., , , , , and . SECRYPT, page 50-58. SciTePress, (2011)