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Experiences with Soft-Core Processor Design., , , and . IPDPS, IEEE Computer Society, (2005)From C to Blokus Duo with LegUp high-level synthesis., , , , , , , , , and 2 other author(s). FPT, page 486-489. IEEE, (2013)FISH: Linux system calls for FPGA accelerators., , and . FPL, page 1-4. IEEE, (2017)Designing an FPGA SoC Using a Standardized IP Block Interface., , , , , and . FPT, page 341-342. IEEE, (2005)A Multithreaded Soft Processor for SoPC Area Reduction., , , and . FCCM, page 131-142. IEEE Computer Society, (2006)A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification., , , , , and . FPL, page 1-6. IEEE, (2006)Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems., , and . HEART, page 12:1-12:6. ACM, (2018)From software to accelerators with LegUp high-level synthesis., , , , , , , , , and 2 other author(s). CASES, page 18:1-18:9. IEEE, (2013)LegUp High-Level Synthesis., , , , , , , , , and . FPGAs for Software Programmers, Springer, (2016)