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Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 383-386. ACM, (2022)

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Memory Exclusion: Optimizing the Performance of Checkpointing Systems, , , , and . Softw. Pract. Exper., 29 (2): 125--142 (February 1999)An evolutionary optimization framework for neural networks and neuromorphic architectures., , , and . IJCNN, page 145-154. IEEE, (2016)Optimizations for a Current-Controlled Memristor-based Neuromorphic Synapse Design., , , , , and . CoRR, (2023)Deploying fault tolerance and taks migration with NetSolve., , , and . Future Gener. Comput. Syst., 15 (5-6): 745-755 (1999)Processor Allocation and Checkpoint Interval Selection in Cluster Computing Systems., and . J. Parallel Distributed Comput., 61 (11): 1570-1590 (2001)Real-Time, Concurrent Checkpoint for Parallel Programs., , and . PPoPP, page 79-88. ACM, (1990)Algorithm-Based Diskless Checkpointing for Fault Tolerant Matrix Operations., , and . FTCS, page 351-360. IEEE Computer Society, (1995)Logistical Networking: When Institutions Peer., , , and . CCGRID, page 446-451. IEEE Computer Society, (2002)Heuristics for optimizing matrix-based erasure codes for fault-tolerant storage systems., , and . DSN, page 1-12. IEEE Computer Society, (2012)Assessing the Performance of Erasure Codes in the Wide-Area., and . DSN, page 182-187. IEEE Computer Society, (2005)