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Disambiguation of "Kaja, Endri"

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Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models.

, , , , , , , and . DFT, page 1-6. IEEE, (2021)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sarah Kajari-Schröder

Two-dimensional Hamiltonian ratchets. Uni Ulm, (2009)

Dilip Babasaheb Kajale

Hans Kaja

Paul Kaja

Endre Kajari

 

Other publications of authors with the same name

PaGoRi:A Scalable Parallel Golomb-Rice Decoder., , , , and . DDECS, page 67-72. IEEE, (2024)Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation., , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2022)Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation., , , , and . MCSoC, page 508-515. IEEE, (2023)MetaFS: Model-driven Fault Simulation Framework., , , , , , and . DFT, page 1-4. IEEE, (2022)Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs., , , and . ISQED, page 1-8. IEEE, (2024)An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods., , , , , , , , , and . ISQED, page 1-8. IEEE, (2024)Bits, Flips and RISCs., , , , , , , , , and 3 other author(s). DDECS, page 140-149. IEEE, (2023)Extending Verilator to Enable Fault Simulation., , , , , and . MBMV, page 1-6. VDE/IEEE, (2021)Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models., , , , , , , and . DFT, page 1-6. IEEE, (2021)Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection., , , , , , and . VLSI-SoC, page 1-6. IEEE, (2022)