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Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables., , and . IEEE Trans. Computers, 55 (8): 1057-1061 (2006)Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery., , , and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1080-1093 (2007)Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory., , , and . MICRO, page 14-27. IEEE, (2020)Deep learning based data prefetching in CPU-GPU unified virtual memory., , , and . J. Parallel Distributed Comput., (April 2023)Exploiting Quantum Assertions for Error Mitigation and Quantum Program Debugging., , , and . ICCD, page 124-131. IEEE, (2022)Locality-Driven Dynamic GPU Cache Bypassing., , , , , and . ICS, page 67-77. ACM, (2015)Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement., , , , , and . ICS, page 433-442. ACM, (2013)An optimizing compiler for GPGPU programs with input-data sharing., , , and . PPoPP, page 343-344. ACM, (2010)yaSpMV: yet another SpMV framework on GPUs., , , and . PPoPP, page 107-118. ACM, (2014)Time-Ordered Event Traces: A New Debugging Primitive for Concurrency Bugs., and . IPDPS, page 311-321. IEEE, (2011)