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Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , и 2 other автор(ы). CoRR, (2021)Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine., , , , , , , , , и 2 other автор(ы). CoRR, (2023)Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2450-2463 (2023)SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions., , , , , и . DATE, стр. 825-830. IEEE, (2022)Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing., , , , , , , , , и . IEEE J. Solid State Circuits, 59 (1): 128-142 (января 2024)Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 57 (1): 127-139 (2022)Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI., , , , и . CoRR, (2020)Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes., , , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 677-690 (2021)Towards Always-on Event-based Cameras for Long-lasting Battery-operated Smart Sensor Nodes., , , , и . I2MTC, стр. 1-6. IEEE, (2021)Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: a low-power accelerator with online learning capability., , , , и . ISLPED, стр. 169-174. ACM, (2020)