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Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST., , , , , и . IEEE Trans. Computers, 65 (8): 2484-2494 (2016)Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection., , и . LATS, стр. 1-6. IEEE, (2022)Novel compensation scheme for local clocks of high performance microprocessors., , , и . ITC, стр. 1-9. IEEE Computer Society, (2007)Novel low-cost aging sensor., , , и . Conf. Computing Frontiers, стр. 93-94. ACM, (2010)Multiple Transient Faults in Logic: An Issue for Next Generation ICs., , , и . DFT, стр. 352-360. IEEE Computer Society, (2005)Accurate Linear Model for SET Critical Charge Estimation., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1161-1166 (2009)Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 238-246 (2017)Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder., , , , , и . J. Electron. Test., 29 (3): 401-413 (2013)Advanced techniques for concurrent fault detection.. University of Bologna, Italy, (2005)The Other Side of the Timing Equation: a Result of Clock Faults., , , , и . DFT, стр. 169-177. IEEE Computer Society, (2005)