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Disambiguation of "Jas, Abhijit"

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Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.

, , , , , and . J. Electron. Test., 29 (3): 401-413 (2013)

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Abhijit Basu

Christian Jas

Abhijit Majumdar

Gerhard Jas

Abhijit Bose

 

Other publications of authors with the same name

Test data compression technique for embedded cores using virtual scan chains., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (7): 775-781 (2004)Weighted pseudorandom hybrid BIST., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (12): 1277-1283 (2004)Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller., , , , and . DFT, page 454-462. IEEE Computer Society, (2008)Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip., and . ICCD, page 418-. IEEE Computer Society, (1999)FPGA-based hardware acceleration for Boolean satisfiability., , , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 33:1-33:11 (2009)Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 466-478 (2010)A low-cost concurrent error detection technique for processor control logic., , , , and . DATE, page 897-902. ACM, (2008)Impact analysis of performance faults in modern microprocessors., , , , and . ICCD, page 91-96. IEEE Computer Society, (2009)Scan Vector Compression/Decompression Using Statistical Coding., , and . VTS, page 114-120. IEEE Computer Society, (1999)Test vector encoding using partial LFSR reseeding., , and . ITC, page 885-893. IEEE Computer Society, (2001)