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Disambiguation of "Nakamura, Hiroshi"

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Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.

, , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2499-2509 (2011)

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Shin'ichiro Nakamura

Makoto Nakamura

Akira Nakamura

Hiroshi Kawabe

Hiroshi Murata

 

Other publications of authors with the same name

On-chip detection methodology for break-even time of power gated function units., , , , , , and . ISLPED, page 241-246. IEEE/ACM, (2011)Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning., , and . ACM Trans. Embed. Comput. Syst., 16 (5s): 181:1-181:21 (2017)Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design., , , , , , and . IEICE Trans. Electron., 96-C (4): 404-412 (2013)Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2301-2308 (2012)Design Method of High Performance and Low Power Functional Units Considering Delay Variations., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3519-3528 (2006)GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications., , , , , , and . PDP, page 135-143. IEEE, (2022)New LDoS Attack in Zigbee Network and its Possible Countermeasures., , , and . SMARTCOMP, page 246-251. IEEE, (2021)Logic Optimization for Asynchronous SI Controllers using Transduction Method., , , and . IWLS, page 245-250. (2002)A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 30 (11): 1157-1164 (November 1995)An asynchronous federated learning focusing on updated models for decentralized systems with a practical framework., , , , and . COMPSAC, page 1147-1154. IEEE, (2023)