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Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.

, , , , and . PDPTA, CSREA Press, (2000)

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Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)., and . FPGA, page 268. ACM, (2012)Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects., , , , and . PDPTA, CSREA Press, (2000)HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4295-4308 (November 2023)Unified data authenticated encryption for vehicular communication., , and . MWSCAS, page 1-4. IEEE, (2016)Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation., , , , , , , and . DAC, page 613-618. IEEE, (2021)Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools., , , and . FPL, page 279-284. IEEE, (2007)Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects., , and . LASCAS, page 1-4. IEEE, (2020)An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model., and . ASP-DAC, page 886-891. IEEE, (2006)ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning., , and . FPL, page 1-11. IEEE, (2016)CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation., , , and . ISCAS, page 1-5. IEEE, (2021)